| 摘要 |
A memory coprocessor architecture and memory arbitration scheme. The coprocessor architecture includes an address generation unit (AGU), a bus control logic unit (BCL) and a combined data cache unit/stack RAM (DCUSR) unit. Each are connected through a memory arbitration unit to a data bus. The memory arbitration unit arbitrates access to the bus by assigning priorities to the coprocessor units. The AGU and the combined DCUSR are mutually exclusive coprocessors which cannot request bus access simultaneously. Hence, the AGU and the combined DCUSR are assigned equal priorities. The BCL is assigned a lower priority and must defer bus access if the AGU or the DCUSR require immediate access. The BCL is provided with a multiple entry queue for storing data temporarily pending access to the queue. A memory scoreboard mechanism is provided such that, if the queue of the BCL becomes full, the BCL can gain immediate access to the bus to allow emptying at least one entry of the queue. The combined DCU and SR share common decoders, sense amps and data paths.
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