发明名称 Planarization process for IC trench isolation using oxidised polysilicon filler.
摘要 <p>Planarising a semiconducting substrate comprises forming flat active area mesas and trenches (31,32,33,34) on the surface, depositing a conformal dielectric, or dielectric precursor, over the face (15) forming depressions above the trenches, and depositing a layer of Si (25) over this. the Si is patterned with photoresist to form resist blocks (30) in the depressions, the Si etched to leave segments beneath these blocks, the Si annealed to convert it to oxide, and the face polished to the tops of the active areas to give a planar surface. Also claimed is a method as above for a Si substrate to which the dielectric is silica, a poly-Si layer is then deposited having a thickness of one-half the depth of the depressions, and the planarisation then proceeds as above.</p>
申请公布号 EP0637071(A2) 申请公布日期 1995.02.01
申请号 EP19940305322 申请日期 1994.07.20
申请人 DIGITAL EQUIPMENT CORPORATION 发明人 NASR, ANDRE ILYAS,;COOPERMAN, STEVEN SCOTT
分类号 H01L21/763;(IPC1-7):H01L21/76 主分类号 H01L21/763
代理机构 代理人
主权项
地址