| 摘要 |
A DRAM having memory cells each consisting of a MOS transistor and a trench-stack capacitor built at a p-type silicon substrate. The MOS transistor comprises a source region made of the first diffused n- layer, and a drain region composed of the first diffused n- layer and the first diffused n+ layer self-aligned with respect to a bit contact hole. At the surface of the p-type silicon substrate is formed a trench penetrating through the source region near the gate electrode of the MOS transistor working also as a word line. The capacitor is built to extend deep into a U-shaped section. The second diffused n- layer is formed at the the trench sidewall surface of the p-type silicon substrate, and the second insulating film is formed over the sidewall of the trench. The second diffused n+ layer is formed at the trench bottom surface of the p-type silicon substrate. The bottom face of the trench functions as a node contact hole of the memory cell. The storage node electrode of the trench-stacked capacitor is electrically connected through the node contact hole, the second diffused n+ layer and the second diffused n- layer to the source region. The structure mentioned above has not only the same effects as the conventional trench-stacked capacitor DRAM over the trench capacitor DRAM but also an effect of less memory cell space than the conventional trench-stacked capacitor DRAM.
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