System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving

摘要

A data processor adopts a CPU that is represented by an RISC type CPU and capable of processing one instruction in one clock cycle. The data processor has an instruction bus and a data bus independently of each other and includes an EPROM connected to the instruction bus and a DRAM connected to the data bus. The RISC type CPU accesses the EPROM with no wait states and the DRAM with one wait state.