| 摘要 |
A circuit that allows an SRAM to automatically switch into low power mode before its power supply voltage input is brought to a lower voltage when the computer is turned off. The circuit includes a device that drives a chip enable input of the SRAM. The device is controlled by a signal indicating whether power is available to the computer system. If the system power is disconnected, the device asserts a low state to the chip enable input of the SRAM. The circuit also includes a device for gradually decreasing the voltage at the power supply voltage input of the SRAM from the system voltage down to the RTC/CMOS memory voltage, which is provided by a separate battery when the computer is shut off. The power supply input voltage is gradually decreased to allow the SRAM enough time to enter into its low power mode. By delaying the switch from the system power supply voltage to the RTC/CMOS memory voltage until it is certain that the SRAM has entered into a low power state, a very small amount of current is drawn from the battery. As a result, the amount of voltage drop across a resistive network connecting the SRAM to the battery is significantly lower, and therefore, the SRAM is able to retain its data.
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