ALGORITHMIC A/D CONVERTER WITH DIGITALLY CALIBRATED OUTPUT

摘要

A multistage pipelined algorithmic A/D converter (34, 36) is digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. The degree of capacitor mismatch is determined through a sequence of measurements for each stage to be calibrated. After the measurements are made the values are stored in a memory device for use during subsequent conversions to cancel the errors due to offset and capacitor mismatch.