| 摘要 |
PURPOSE:To reduce the frequency switching time by providing a frequency synthesizer of PLL configuration employing a VCO to a feedback loop, providing a clock fCLK obtained through frequency division of the VCO output, and increasing the arithmetic operation speed of the numerical control oscillator which integrates a phase incremental step DELTAphi set and received externally to provide an output of a feedback phase signal phi. CONSTITUTION:The oscillator is provided with a frequency divider 16 providing an output of clocks fCLK/4 and fCLK/2 from an input clock fCLK. A phase incremental step DELTAphi is given to an adder 11, and the adder 11 and a register 12 calculates the DELTAphi based on the clock fCLK/4. The output SIGMA4DELTAphi being one input and outputs of adders 17, 18, 19 being other input resulting from addition of outputs -DELTAphi, 2DELTAphi from multiplier circuits 13, 15 are given to a register 20, in which 4-phase parallel arithmetic operation is executed in the timing of the fCLK/4, a multiplexer 21 implements parallel/serial conversion and a register 22 provides an output of a feedback phase signal phi according to the fCLK. |
