发明名称
摘要 PURPOSE:To smoothly perform a restoring operation by stopping each of a DMA controller, an error correcting circuit, and a formatter with its own operation error signal and an operation error informing signal from the others. CONSTITUTION:The DMA controller 4, the error correcting circuit 6, and the formatter 7 constituting a controller 1 are internally provided with operation abnormality processing circuits 4a, 6a, and 7a respectively. If one of operation abnormality processing circuits 4a, 6a, and 7a detects the operation error in its own circuit, it stops its own operation at a prescribed timing and informs the other circuits of the occurrence of operation error. In being informed of the occurrence of operation error, the other operation abnormality processing circuits stop their operation at a prescribed timing. Contents of the error are read into a microcomputer 3 to perform the recovery operation.
申请公布号 JPH0682318(B2) 申请公布日期 1994.10.19
申请号 JP19890312585 申请日期 1989.11.30
申请人 VICTOR COMPANY OF JAPAN 发明人 YAMAGISHI TOORU;TANAKA KOJI
分类号 G06F3/06;G06F11/00;G11B19/02;G11B20/18 主分类号 G06F3/06
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