| 摘要 |
PURPOSE:To reduce the parallel resonance of the inductance of a conductor pattern and the parasitic capacitance between the conductor and ground to eliminate peaks and dips in characteristic curves of an optical module by inserting a chip capacitor between an optical element and ground for decreasing the impedance of a bias source. CONSTITUTION:A ground layer 11 is formed on a surface of a chip carrier 12 where a photodetector is attached. A capacitor 3 is placed between the photodetector 1 and the ground layer 11. Since C1 makes an a.c. short circuit, the parallel resonance of C1, L2, ST2 and LB is prevented, thus eliminating dip B. If C1 is increased, Q of a peak A due to the series resonance of LB, ST1, L1, and C3, CA, C1 is lowered, thus lowering peaks. The dielectric layer under striplines of the chip carrier 12 is made thin to decrease the stripline- ground capacitance so that the width of the stripline may be optimized. |
