| 摘要 |
PURPOSE:To provide plural connections without reducing transfer width between processors, and to realize interlaced transfer jumping over several processors. CONSTITUTION:Network switching circuits (SE) 109 to 116 are installed between adjacent interconnection switches (EX) 105 to 108. SE is connected to the adjacent interconnection switch by a data line, and simultaneously, it is connected to SE distant by plural stages by the data line, and when a network switching signal from a host computer instructs adjacent transfer, it transfers data inputted from the data line to adjacent EX, and at the time of the instruction of the interlaced transfer, it transfers the data to SE distant by plural stages. When the network switching signal instructs the adjacent transfer, it separates the data, and sends it to the data line to adjacent EX and the data line to SE, and at the time of the instruction of the interlaced transfer it sends all the data to the data line to ES. |
