发明名称 Circuit arrangement for multiplication of elements in a finite Galois field (2<8>)
摘要 A Galois field multiplier for a finite Galois field GF (2&lt;8&gt;) is proposed. In it, Galois field elements are fed on first parallel lines (A0 to A7) as a first factor to a first EXOR network (101 to 127). Intermediate results (Enn), which are output at the output of the EXOR network (101 to 127), are ANDed in a one-stage AND network (x00 to x77) with second Galois field factors which are transmitted on second lines (B0 to B7). The products of the input elements can be taken from third lines (P0 to P7) in a three-stage EXOR network (201 to 207) which is connected in series. &lt;IMAGE&gt;
申请公布号 DE4303644(A1) 申请公布日期 1994.08.11
申请号 DE19934303644 申请日期 1993.02.09
申请人 PHILIPS PATENTVERWALTUNG GMBH, 20097 HAMBURG, DE 发明人 MESTER, ROLAND, DIPL.-ING., 6100 DARMSTADT, DE
分类号 G06F7/72;(IPC1-7):G06F7/52 主分类号 G06F7/72
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