发明名称 |
Semiconductor integrated circuit protected from element breakdown by reducing the electric field between the gate and drain or source of a field effect transistor |
摘要 |
A semiconductor integrated circuit which is protected from element breakdown includes a memory cell, series-connected first and second program load transistors arranged between the memory cell and the program power source, a boosting circuit for outputting a board voltage higher than the voltage of a program power source, and a controller. The controller applies the boosted voltage to the gates of the first and second program load transistors when program data is set at a first logic level. The controller applies a voltage of about 0 V to the gate of the first program load transistor and an intermediate voltage lower than the voltage of the program power source and higher than 0 V to the gate of the second load transistor when the program data is set at a second logic level.
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申请公布号 |
US5336952(A) |
申请公布日期 |
1994.08.09 |
申请号 |
US19930067102 |
申请日期 |
1993.05.26 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
IWAHASHI, HIROSHI;FUJIMOTO, TOSHIYUKI;NARITA, AKIRA |
分类号 |
G11C17/00;G11C5/14;G11C8/08;G11C16/06;G11C16/12;H03K17/10;(IPC1-7):H03K17/687 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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