发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To provide a semiconductor integrated circuit capable of efficiently judging normal/defective conditions even when the number of the external terminals of the semiconductor integrated circuit and its function are limited. CONSTITUTION:This semiconductor integrated circuit incorporates an inspecition circuit 3 provided with a parity checking circuit 7 for inputting the output pattern data 5 of a circuit block 2 for which input pattern data 4 for testing are supplied to be operated and parity data 6 supplied from an outside and performing parity checking in order to judge the normal/defective conditions of the circuit block 2 for realizing the prescribed function and an output circuit 8 for inputting output signals outputted from the parity checking circuit 7 and changing an output logical value at the time of taking a logical value for meaning parity check abnormality. |
申请公布号 |
JPH06180656(A) |
申请公布日期 |
1994.06.28 |
申请号 |
JP19920353282 |
申请日期 |
1992.12.11 |
申请人 |
HITACHI LTD |
发明人 |
HABUKA TOSHITO;YANAGISAWA YOSHIAKI;OSAWA HIROTAKA;HAIJIMA MIKIO;KUBO SEIJI |
分类号 |
G06F11/10;G06F11/22 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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