| 摘要 |
Reset, clamp, and sample pulses for a CCD sensor for electronic imaging applications are generated which have their leading edges delayed with respect to the leading edges of corresponding pixel clock pulses by substantially constant proportions of the pixel clock period independently of pixel frequency. To do this, a first auxiliary 50 percent duty cycle pulse train is generated having a frequency 4 times the pixel frequency. A divide by 4 counter receives the first auxiliary train and produces both the pixel clock itself and a second auxiliary 50 percent duty cycle pulse train having a frequency twice the pixel frequency. A 3 to 8 line decoder receives the pixel clock and both auxiliary trains to produce eight separate trains of pulses having the pixel frequency and a substantially 12.5 percent duty cycle. Each of the eight separate trains has the leading edge of its pulses delayed by substantially an eighth of the pixel clock period from the leading edge of the pulses of a different one of the eight separate trains. Different ones of the eight separate rains are selected to form the desired trains of reset, clamp, and sample pulses.
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