发明名称 DIGITAL DEMODULATION CIRCUIT
摘要 PURPOSE:To reduce the delay of the entire phase synchronizing loop, to expand the frequency area where the phase synchronization is available, and to reduce the phase jitter after leading in. CONSTITUTION:A quasi-synchronizing orthogonal detection circuit 51 converts an input digital modulation wave into the component of each orthogonal phase axis and performs frequency conversion. The conversion output is digitized by A/D converters 56 and 58. The digitized output is phase-detected by a complex multiplier 60, and the demodulation output is obtained by symbol detecting devices 62 and 63 from the detection output. In a phase comparator 64, the phase difference between a symbol and the prescribed phase axis is detected. The phase difference output is supplied through a filter 65 to the frequency control terminal of a numeric control oscillator 66. The oscillation output of the numeric control oscillator 66 is supplied to the complex multiplier 60 as the signal of the detection axis. In this case, the operation clock frequency of the phase comparator 64, filter 65, numeric control oscillator 66, and complex multiplier 60 are made integral multiple more than double of the operation clock of the A/D converters 56 and 57.
申请公布号 JPH06120997(A) 申请公布日期 1994.04.28
申请号 JP19920266137 申请日期 1992.10.05
申请人 TOSHIBA CORP;TOSHIBA AVE CORP 发明人 SUGITA YASUSHI;ISHIKAWA TATSUYA;TAGA NOBORU;KOMATSU SUSUMU
分类号 H04L7/00;H04L7/027;H04L27/22;H04L27/38 主分类号 H04L7/00
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