High-speed address transition detection circuit

摘要

An address detection transition circuit provides an address transition detection pulse in response to either a high-to-low or a low-to-high external address input logic transition. The address transition detection circuit includes an address input buffer that responds to the external address input by providing first and second complimentary signals at first and second address input buffer output nodes, respectively. A first delay chain connected between the first address input buffer output node and the buffer output node responds to a high-to-low external address input logic transition by providing a logic high signal at the buffer output node. Similarly, a second delay chain connected between the second address input buffer output node and the buffer output node responds to a low-to-high external address input logic transition by providing a logic high signal at the buffer output node. A pull-down device responds to a logic high signal at the buffer output node by generating a logic low address transition detection pulse at the address transition detection node. A feedback controlled network connected to the address transition detection node controls the pulse width of the address transition detection pulse.