发明名称 Semiconductor memory having stacked capacitors and MOS transistors
摘要 A dynamic random access memory comprises a p-type semiconductor substrate and a plurality of first n-type diffused regions embedded in the substrate so that they extend along a first axis of the substrate parallel with first and second, opposed major surfaces of the substrate to form parallel bit lines. A matrix array of insulated gate electrodes extend along a second axis of the substrate normal to the first axis from the first major surface into the first n-type diffused regions, so that those of the insulated gate electrodes which are arranged along rows of the matrix are connected together by the parallel bit lines. Second n-type diffused regions are embedded in the substrate adjacent to the first major surface as well as to corresponding ones of the insulated gate electrodes. Parallel conductors extend along a third axis of the substrate for electrically connecting those of the gate electrodes which are arranged along columns of the matrix array to respective word lines, the third axis being perpendicular to both of the first and second axes. Capacitors are stacked on the insulated gate electrodes, respectively. Each of the capacitors has a cell electrode coupled to one of the second n-type diffused regions, a common electrode and a charge storage layer interposed therebetween.
申请公布号 US5307310(A) 申请公布日期 1994.04.26
申请号 US19910743238 申请日期 1991.08.09
申请人 NEC CORPORATION 发明人 NARITA, KAORU
分类号 H01L27/04;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L29/78 主分类号 H01L27/04
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