发明名称 |
Method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate |
摘要 |
A method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate comprises the steps of: a) patterning a structure of a layer of silicon formed on an insulating substrate to form first, second, third, and fourth silicon islands; b) doping the second island with a p-type dopant; c) doping the third island with a p-type dopant; d) doping the fourth island with an n-type dopant; e) forming a first electrically insulating gate layer on the third and fourth islands; f) forming a second electrically insulating gate on the first and second islands; g) forming an electrically conductive gate over the first and second electrically insulating gate layers; h) doping the second island with an n-type dopant; i) doping the fourth island with an n-type dopant; j) doping the first and third islands with a p-type dopant; and k) doping the first and third islands with a p-type dopant to transform the first island into a p-type enhancement mode field effect transistor, the second island into a n-type enhancement mode field effect transistor, the third island into a p-type depletion mode field effect transistor, and the fourth island into an n-type depletion mode field effect transistor.
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申请公布号 |
US5300443(A) |
申请公布日期 |
1994.04.05 |
申请号 |
US19930094541 |
申请日期 |
1993.06.30 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY |
发明人 |
SHIMABUKURO, RANDY L.;WOOD, MICHAEL E.;CSANADI, OSWALD I. |
分类号 |
H01L21/8238;H01L21/84;(IPC1-7):H01L21/265 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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