| 摘要 |
PURPOSE: To provide a DRAM architecture realizing high speed sensing by using plural sense amplifiers with a single local differential amplifier. CONSTITUTION: A main input/output I/O line is arranged between cell arrays and a cell array 120 has the plural sense amplifiers S/A. The selection of the amplifiers S/A is managed by a signal from a sense amplifier selection line and the selection line transmits a high level signal to the gate of an N channel transistor Tr 14. Thus, the specified amplifier S/A is selected. A logic high level signal on a section selection line turns on Tr 121 and N channel Tr 128 and 130 which are symmetrically arranged are provided. Information is transmitted to the sense amplifier or from the sense amplifier through a local differential amplifier connected to a P channel load Tr 134. Thus, the DRAM architecture which can realize high speed sensing can be obtained. |
