发明名称 |
Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors |
摘要 |
Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide in the MOS structure. In such MOS structures, the silicon-enriched oxide layer may be disposed immediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination of these locations. Each silicon-enriched oxide layer preferably contains at least about 1017 per cm3 dangling bonds.
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申请公布号 |
US5290727(A) |
申请公布日期 |
1994.03.01 |
申请号 |
US19920860370 |
申请日期 |
1992.03.30 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
JAIN, VIVEK;PRAMANIK, DIPANKAR;NARIANI, SUBHASH |
分类号 |
H01L21/8247;H01L21/314;H01L21/316;H01L21/8244;H01L23/29;H01L23/532;H01L27/11;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/70 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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