| 摘要 |
<p>A system and method accurately translate a structural data file (30) that describes a complex logic circuit into a simulation model file (40) executable by a simulator (42). A net-list (34) is traversed, and the resulting model description is compiled into structural partitions including a WHEN-CONDITION partition (WC) that identify boundaries between synchronous and asynchronous subcircuits. The simulation model is also divided into execution time levels by a partitioned levelization method. Asynchronous feedback loops, which ordinarily lead to levelization failures, are correctly modeled by inserting time delay 'levelers' (254, 262) into the feedback loop model. The resulting simulation model includes re-evaluation and evaluation stability checking steps (152, 230, 232, 276) that provide correct functional and timing evaluation of the simulation model.</p> |
