| 摘要 |
<p>A clock distribution circuit (Fig. 1) with drivers (11) distributing a clok signal on multiple paths (15) has de-skewing circuitry for equalizing the total clock delay to the different clock recipient circuits (17) in a system. The de-skewing logic uses a return path (29) parallel to the outward path (15) to sense the propagation delay and includes a phase comparator (63) receiving the return signal (59) and a reference signal (61) for comparison of their phase. Voltage-controlled delay elements (47, 49), responsive to a control voltage (51) provided by a charge pump (69) controlled by the phase comparator, adds or removes equal amounts of delay to the outward and return paths until the return signal phase matches that of the reference signal. In one embodiment (Fig. 4) the de-skewing circuitry for each driver (71, 73) time-shares a common phase comparator (75) and charge pump (77), using sample-and-hold circuits (113, 115) to store the control voltages obtained by the comparisons. Receivers (37) on the return paths may have selectable input buffers (39, 41) to take into account the buffer delays of different logic family types of the clock recipients.</p> |
