| 摘要 |
<p>PURPOSE:To perform continuous access to memory by inactivating an access control signal earlier than a timing proper to a processor. CONSTITUTION:An address signal instructing a part to be accessed is instructed on an address bus 7 from the processor 1, and it is transmitted to memory 2, a memory control circuit 6, and an address comparator 4. Simultaneously, a processor strobe signal 9 representing the validity of the address is activated, and is sent to a strobe control circuit 5. The strobe control circuit 5, when a comparison decision signal 8 being activated, activates a strobe signal 10 at a timing set in advance in an inactive state regardless of the activated state of the processor strobe signal 9 from a processor part 3. When the strobe signal 10 is inactivated, a memory selection signal 11 is inactivated via the memory control circuit 6.</p> |
