| 摘要 |
In a process for fabricating an integrated circuit (IC) by simultaneously forming field-effect transistors (FETs) and bipolar junction transistors (BJTs) in a semiconductor substrate, a method of reducing the junction capacitance of said FETs (30, 40) comprising the steps of: (a) defining active regions for said BJTs and FETs in said substrate; (b) forming a gate oxide over said substrate; (c) forming gate members of said FETs above said gate oxide; (d) implanting an impurity into said substrate to form well compensation regions (45, 46) therein, said well compensation regions being self-aligned to the source and drain regions (54, 53) said FETs and acting to reduce said junction capacitance in said IC. <IMAGE> |
