发明名称 FRAME SYNCHRONIZATION CIRCUIT
摘要 PURPOSE:To improve the synchronization restoration characteristic and to decrease the worst average synchronization restoration time by providing a synchronization pattern detection circuit simultaneously discriminating coincidence/anticoincidence between r-bits in total arranged at an n-bit period in a received data string and r-kinds of predetermined r-bit synchronization patterns to the title circuit. CONSTITUTION:Received data in 6-bits received from a reception data input terminal 51 and outputted from a shift register 1 at an interval of 772 bits are inputted to an input terminal of a synchronization pattern detection circuit 2 as parallel data. When the 6-bit reception data outputted from the shift register 1 are coincident with any of synchronization pattern among in total 6 kinds of patterns as 001011, and 100101, 110010, 011001, 101100,010110 resulting from bit-shift right of the pattern 001011, an output signal X whose level is '1' representing the coincidence is outputted from its output terminal to a control circuit 3. In the case of anticoincidence, an output signal X whose level is '0' representing the anticoincidence is outputted from its output terminal to the control circuit 3.
申请公布号 JPH05304519(A) 申请公布日期 1993.11.16
申请号 JP19920080205 申请日期 1992.04.02
申请人 NEC CORP 发明人 OKANE SHOJI
分类号 H04L7/08;H04J3/06;H04Q11/04 主分类号 H04L7/08
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