| 摘要 |
A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.
|
