| 摘要 |
PURPOSE:To confirm normalness of the high speed processing mechanism in a processor of an information processing system provided with a control register for controlling the speed increasing mechanism such as cache memory, a pipeline. CONSTITUTION:A test program is constituted of a state setting processing part 20 for transferring the high spped processing mechanisms 13-15 to an invalid/valid state, a test executing part 21 for executing an actual test instruction train, and storing a result of execution, and an execution result comparing part 25 for comparing the result of execution, and by the state setting processing part 20, a state of the mechanisms 13-15 is set to an invalid state, the test instruction train is executed by the test executing part 21, and its result is stored in a prescribed result store area (1). Subsequently, by the state setting processing part 20, the mechanisms 13-15 are set to a valid state, the test instruction train is executed by the test executing part 21, its result is stored in a different result store area (2), and by the execution result comparing part 25, it is confirmed that the result of execution (1) at the time when the mechanisms 13-15, and the result of execution (2) at the time when the mechanisms 13-15 are valid coincide with each other. |
