发明名称 CLOCK PHASE CONTROL SYSTEM FOR TDMA COMMUNICATION
摘要 PURPOSE:To provide the clock phase control system of a TDMA (time division multiaccess) communication by which a line setting can be attained by matching the phase of the clock of a slave station with the phase of the reference clock of a master station in a short time. CONSTITUTION:Phase matching data transmitted from a slave station by the arbitrary phase of the slave station clock from a slave station clock generation part 1, are receive by the master station, and a received signal waveform is converted into a peak detection waveform indicating the peak of a signal by a peak detecting part 9. Then, the peak detecting waveform and the signal waveform of a master station reference clock from a master station reference clock generating part 6 are inputted to a phase deviation detecting part 8 in order to search the phase deviation of the slave station clock, the feedback of the phase deviation data to the slave station clock generating part 1 is operated, and the phase of the slave station clock can be matched with the phase of the master station reference clock.
申请公布号 JPH05276130(A) 申请公布日期 1993.10.22
申请号 JP19920100183 申请日期 1992.03.27
申请人 发明人
分类号 H04B7/26;H04J3/00;H04J3/06;H04L27/18 主分类号 H04B7/26
代理机构 代理人
主权项
地址