发明名称 CLOCK GENERATION CIRCUIT
摘要 <p>PURPOSE:To perform both operations of a reload timer and arbitrary duty factor clock generation by attaching the function of a reload timer circuit and that of an arbitrary duty factor clock generation circuit on a clock generation circuit. CONSTITUTION:A data register 1 writes the data of preset count value at every bit, and holds and outputs it, and also, a counter 2 performs a counter operation at every input of a count clock CL0. A comparator 3 compares the preset count value in the data register 1 with the count value of the counter 2, and outputs a coincidence signal F when coincidence is obtained between them, and a full- count detection circuit 4 outputs a full-count signal E when the count value of the counter 2 overflows. A reset circuit 5 resets the count value of the counter 2 at every output of the coincidence signal F in the operation of the reload timer, and at every output of the full-count signal E in the operation of the duty factor clock generation.</p>
申请公布号 JPH05265588(A) 申请公布日期 1993.10.15
申请号 JP19920060149 申请日期 1992.03.17
申请人 发明人
分类号 G06F1/06;G06F1/14;(IPC1-7):G06F1/06 主分类号 G06F1/06
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