A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.
申请公布号
US5247655(A)
申请公布日期
1993.09.21
申请号
US19890432680
申请日期
1989.11.07
申请人
CHIPS AND TECHNOLOGIES, INC.
发明人
KHAN, RASHID N.;CHEN, CHENG;CHENG, CHIEN-FENG;VERSTEGEN, BRIAN;CHENG, WIN-SHENG;GOLLABINNIE, AURAV