Phase control circuit for clock signal regeneration from data signal - has two logic links with inputs fed with data signal and (non)inverted clock signal

摘要

The circuit contains a phase comparator (9) of logic link circuits (21, 22). To the inputs of the latter is supplied a data signal, prepared by a flank detector (7), and a clock signal from a VCO (10). Output signals of the logic link circuits are passed through a narrow band loop filter (23-28) and supplied to inputs of an amplifier assembly (29-34) with Pi transmission characteristic. The amplifier assembly contains an offset. At one input of the amplifier assembly is coupled a comparator (35) with a hysteresis, which couples a filter output signal with fixed potential via a change-over switch (36). The two logic links are pref. NOR-gates, each with two inputs. USE/ADVANTAGE - For transmission of NRZ data signals, with reliable operation.