| 摘要 |
PURPOSE:To provide a serial/parallel (S/P) conversion circuit capable of easily executing rapid processing without considering of a margin due to a clock delay or the like, matching the timing of data changes and easily processing parallel data as a S/P conversion circuit for converting serial data into parallel data. CONSTITUTION:The S/P conversion circuit for converting serial data into n-bit parallel data is provided with a shift register 1 having plural n-bit parallel output for inputting serial data, n D-flip flops (FFs) 21 to 23 for inputting a shift clock from the register 1 as a trigger signal and plural selectors 31 to 33 for inputting the outputs of the D-FFs 21 to 23 and respective parallel outputs from the register 1 as each two inputs and selectively outputting either one of the two inputs to apply the selected input to each of the D-FFs 21 to 23 as a data input. The selectors 31 to 33 select the outputs of the register 1 at the rate of once to n shift clocks to convert the outputs of the D-FFs 21 to 23 and output the converted results in parallel. |
