发明名称
摘要 PURPOSE:To attain execution of instruction by starting from the prescribed instruction by setting a flip-flop when a microprocessor is reset and obtaining the contents of an operation register which are different from those of a stop microinstruction. CONSTITUTION:A flip-flop 5 which produces the stop release bit is provided together with AND gates 6 and 8 and an OR gate 7. The gate 8 produces an output in case the contents of an operation register 3 are equal to '0' and the stop release bit is produced. The gate 7 produces an output by the output of the gate 8 and other input conditions. Furthermore, the gate 6 supplies the clocks to a control storage address register 1 as well as to the register 3 for execution of a microprogram. Such an execution is usually started at and after the '0' address of a control storage 2 and a NOP instruction, for example, is carried out.
申请公布号 JPH0559449(B2) 申请公布日期 1993.08.31
申请号 JP19860055553 申请日期 1986.03.13
申请人 FUJITSU LTD 发明人 KARIBE HIDENORI;YOSHIDA SHOICHI;SHIMAKURA KAZUKO
分类号 G06F9/22;G06F11/00;G06F11/14 主分类号 G06F9/22
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