| 摘要 |
A computer bus for transferring data among a plurality of modules coupled thereto, and having flexible, distributed bus arbitration. A plurality of data lines is operable to transfer bits of data among modules attached to the bus. A single arbitration line is coupled to each module, and is used to indicate whether the bus is available for the next bus cycle. A bus packet clock, called a BUP clock, is used to divide the bus into cycle periods called BUP time slots. An access time clock further divides these BUP time slots into time access slots. The BUP time slot is the unit of time for which a module will be granted access to the bus. The BUP time slot is selected so that modules will be granted access to the bus for a length of time defined by a packet length. Each module on the bus is provided with arbitration circuitry for determining whether that module will be granted access to the bus for the next BUP time slot. The arbitration circuitry counts the number of accessed time slots and compares the counter value to a module priority value and outputs a comparison time pulse when the values compare. A module with a lower priority number will pull the arbitration line low and claim the bus for the next BUP time slot if this module is requesting the bus for the next BUP time slot. Once a module has pulled the arbitration line low, no other module will be granted access to the bus for the next BUP time slot. When the next BUP time slot occurs, the module granted access to the bus for that period will be given access, and the counters of each module will be reset, and the priority of each module updated. |
