| 摘要 |
A parallel scrambling system comprises an M-bit (M>1) interleaved parallel scrambler (21) for parallel scrambling input signals (A0, A1, A2... ) and an M-bit interleaved multiplexer (22) for multiplexing output signals from the M-bit interleaved parallel scrambler. With this arrangement, an M-bit interleaved parallel scrambling of input signals is carried out prior to a multiplexing thereof. The parallel scrambling system also comprises an M-bit interleaved demultiplexer (24) for receiving a parallel scrambled and multiplexed signal from the M-bit interleaved multiplexer and demultiplexing it and an Mbit interleaved parallel descrambler (26) for descrambling output signals from the demultiplexer to make original signals recover. As the scrambling of input signals is carried out prior to the multiplexing thereof, the scrambler can be operated at the rate identical to the transmission rate of input signals, thereby reducing the manufacture cost and electric power consumption to a minimum. <IMAGE> |
