| 摘要 |
PURPOSE:To attain the reduction processing with simple configuration while keeping its intermediate tone even when a picture of a pseudo intermediate tone is reduced. CONSTITUTION:An interleave signal generating circuit 1 generates an interleave signal in a timing corresponding to the reduction rate. Picture element data in an original picture are sequentially inputted to a shift register 2 along the main scanning direction. In this case, when no interleave signal is entered, the inputted picture element data are inputted by all bits and when the interleave signal is entered, after picture element data of a just preceding time are shifted and the inputted picture element data are inputted to a least significant bit and the result is outputted. The output is inverted by an inverting circuit 3 and a reference value (threshold value) and the output of the inverting circuit 3 are compared by a comparator 4 and a binary value is converted into '1' or '0' level therein. The binary data are latched or deleted in a register 5 at a timing of the interleave signal and the result is reduced then by an interleave circuit 6, in which the interleaved picture element data are stored by a prescribed ratio. |
