发明名称 IMAGE DATA REDUCTION SYSTEM
摘要 PURPOSE:To reduce the image data at a high speed by connecting together the reduced data adjacent to each other after shifting these data by an extent equivalent to the number of bits by a prescribed reduction ratio. CONSTITUTION:The 16-bit image data are applied to an OR arithmetic circuit contained in 8 microprocessor, and the OR arithmetic circuit performs the OR addition of 0-bit and 1-bit data to obtain the 0-bit data. The 2-bit-4-bit data ere directly used as the 1-bit-3-bit data, the 5-bit and 6-bit data are turned into the 4-bit data by the OR addition, the 7-bit-9-bit data are directly used as the 5-bit-7-bit data, the 10-bit and 11-bit data are turned into the 8-bit data by the OR addition, and the 12-bit-15-bit data are directly used as the 9-bit-12-bit data respectively. Meanwhile the 16-bit data which is reduced by a CPU with addition of the zero data is stored in three remaining bits to which no data are added. These various types of processing are carried on to process the entire image data for each row.
申请公布号 JPH05189558(A) 申请公布日期 1993.07.30
申请号 JP19920123576 申请日期 1992.05.15
申请人 CASIO COMPUT CO LTD 发明人 SONE MASASHI
分类号 G06F3/153;G06T3/40;G09G5/36;H04N1/393 主分类号 G06F3/153
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