发明名称 A cache controller.
摘要 <p>A hierarchical cache memory system (10) efficiently determines inclusion and insures data coherency between two or more memory arrays (16, 18, 22). In memory system (10), a secondary cache (18) stores secondary cache information in a first memory (34) and primary cache inclusion information in a second memory (36). Memory (36) stores only a portion of an information value stored in a primary cache (16) and uses that portion as an index to indicate whether the information value is included in primary cache (16). A second level cache tag value is compared to a first portion and an index is compared to a remaining portion of the information value stored in primary cache (16) using a comparator (38, 40, 42). A logic circuit (44) processes an output of the comparator (38, 40, 42) to determine whether the information value is included in primary cache (16).</p>
申请公布号 EP0549219(A1) 申请公布日期 1993.06.30
申请号 EP19920311365 申请日期 1992.12.14
申请人 MOTOROLA, INC. 发明人 BEAVERS, BRADFORD B.;REED, PAUL A.;SLATON, JEFF A.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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