| 摘要 |
Method and device for generating synchronised signals (SS1, ...) which are necessary for the justification (and dejustification) of the binary train of a secondary tributary at a low data rate sent in a higher-level frame. These signals originate from a programmable memory (M1), the high addresses (Ax-3,..., Ax) of which are supplied by a coder wheel (R1), and the lower addresses of which (A1, A2,..., Ax-4) are supplied by a synchronous counter (C1), which is advanced by the clock signal (1) and zeroed by the frame synchronisation signal (2). <IMAGE>
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