| 摘要 |
The image data in the decoding state is stored directly into an image memory by the controller when coding the image data. The document image compression/expansion on processor (DICEP) controller reads and decodes the stored image data so that the image data in the image memory is accessed with high speed. The circuit comprises a controller generating the first address for storing the data and the second address for coding, a decoder generating the first and second enable signals after decoding the first and second addresses, a dual port memory controller forming the data passway, and a DICEP coding the decoding data stored in the image memory and storing the decoded image data into the image memory.
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