发明名称 FAULT DETECTING CIRCUIT
摘要 PURPOSE:To improve reliability by checking operational correctness of a functional circuit by means of inoperative timing check for a circuit, in addition, separately reporting that result from a detective report during operation. CONSTITUTION:A parity predicting circuit 112 is applied with outputs P0 and P1 of registers 102 and 104 which correspond to operands D0 and D1 so as to generates and outputs a parity P2 corresponding to an arithmetic result D2. A parity check circuit 113 checks correct relation between the arithmetic result D2 and the output P2 of the parity predicting circuit 112. If the relation between data, that is the arithmetic result D2, and a parity, that is the output P2, comes to mean coincidence, then '0' is outputted, and if it means uncoincidence, '1' is outputted. A register 105 sets an arithmetic circuit 111 to '1' at an effective data supplying timing. At an register 123, a fault report is set by an AND gate 114 at an effective timing. In that cace, at a register 124, a fault report is set by an AND gate 115 at an ineffective timing of the arithmetic timing 111.
申请公布号 JPH0528001(A) 申请公布日期 1993.02.05
申请号 JP19910202522 申请日期 1991.07.17
申请人 KOUFU NIPPON DENKI KK 发明人 NAKAMURA TOSHIHIKO
分类号 G06F11/22;G06F11/34 主分类号 G06F11/22
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