Parallel processor with branching delay slot for instructions - has queuing memory connected to instruction output analyser and branching processor circuits with flag control section

摘要

A superscalar processor, fetching and detecting several instructions simultaneously for distribution to corresp. functional units, transfers instructions to a queue (13) of several blocks. Instructions in the same block as the branching instruction and in an adjoining block form the branching delay slot. The queue has a number of entries each including an instruction with a flag indicating its relationship to a branching forecast. This flag determines execution or non-execution of the instruction with which it is associated. ADVANTAGE - Power of parallel processing unit is not degraded by branching.