FEHLERKORREKTURVERFAHREN UND ANORDNUNG FUER CHIPS MIT MULTIBITAUSGABE.
摘要
An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.
申请公布号
DE3586851(D1)
申请公布日期
1993.01.07
申请号
DE19853586851
申请日期
1985.06.03
申请人
INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人
AICHELMANN, JR., FREDERICK JOHN, HOPEWELL JUNCTION NEW YORK 12533, US;LANGE, LAWRENCE KENNETH, WAPPINGERS FALLS NEW YORK 12590, US
