| 摘要 |
A process for manufacturing thin film transistors that have small source-drain areas, small gate-source parasitic capacitance Cgs, and low contact resistance, comprising producing the gate of the transistor on a glass substrate, depositing a gate insulating layer, a thick undoped amorphous silicon layer and a top passivation layer successively on the substrate. The top passivation layer and the thick undoped amorphous silicon layer are then etched until the insulating layer is exposed.
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