DEVICE FOR CONTROLLING BUS.

摘要

A device for controlling buses which reduces the time for waiting bus accesses and particularly improves the performance of an arithmetic processing means which frequently access a main memory. The device is provided with a means (12b) for generating a bus request signals in response to the requests from an arithmetic processing means (12a), a means (e) for arbitrating the rights of using the buses which arbitrates the rights of using the buses in response to the bus request signals and informs the unit of the result, a means (12c) for performing bus accesses using the means (12a) as a bus master after receiving the information on the right of using the buses, and a hold indicating means (12d) for making the bus request signals held while a predetermined hold signal is asserted and a predetermined release signal is negated.