| 摘要 |
<p>PURPOSE: To provide circuit arrangement for repeatedly decelerating the execution of the program of a microprocessor so that low speed data can be exchanged with a low speed outside memory. CONSTITUTION: A frequency-dividing device is connected with the clock input terminal of a microprocessor, a clock frequency is decreased in a part of the operating cycle of the microprocessor enabling access to an outside device by this frequency dividing device, and operation is executed by the maximum clock frequencies in the remaining parts of the cycle. The decrease of this clock frequency is always operated even when the access is not actually performed so that the mean clock frequency of the microprocessor can be constant, and an inside timing means can use the clock signal as it is. The frequency-dividing device is provided with plural counters 30, 34, 36, and 38, and those counters count the prescribed number of clock pulses by using a clock signal received by an input terminal CL, reaches a final position after the prescribed number of counts, and outputs an output signal to a carry output terminal.</p> |
