发明名称 |
IDENTIFYING CLOCK PHASE GENERATING SYSTEM |
摘要 |
<p>PURPOSE:To detect an optimum switching position between a fixed identification clock and an adaptive identification clock. CONSTITUTION:A generating signal of an adaptive identification clock generating circuit is selected and outputted by using a fixed identification clock generating circuit 2 generating a fixed identification clock after a 1st time t1 from a trailing edge of a frame bit F, an adaptive identification clock generating circuit 4 generating an adaptive identification clock generated after a 2nd time t2 by taking a signal delay between a master station TN and a slave station TE into account, and a clock selection circuit 5 when the 2nd time t2 is delayed more than the 1st time t1.</p> |
申请公布号 |
JPH04280527(A) |
申请公布日期 |
1992.10.06 |
申请号 |
JP19910067794 |
申请日期 |
1991.03.08 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
SHIBANO YUKIO;YAMANO SEIICHI |
分类号 |
G06F1/12;H04L7/08 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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