摘要 |
<p>An object of the present invention is to miniaturize a structure of a memory cell in an SRAM. The memory cell in the SRAM includes a pair of access transistors {Q3 (Q4)}, a pair of driver transistors {Q1 (Q2)} and a pair of load transistors {Q5 (Q6)}. The six transistors are thin film transistors. A plurality of thin film transistors are provided on a surface of a silicon substrate (32), forming a plurality of layers with an interlayer insulating layer (33a, 33b) interposed therebetween. <IMAGE></p> |