| 摘要 |
<p>PURPOSE:To realize the circuit system able to transfer an HDLC data in the asynchronous mode though the addition of a simple circuit without need for a special asynchronous mode/synchronous mode conversion circuit with respect to the data transfer system in the asynchronous mode between communication LSIs in which the HDLC data is converted into an MRZI and only the HDLC data is sent/received while idle time between data is filled by a prescribed flag. CONSTITUTION:A clock extraction device 1 receiving an HDLC transmission data D1 and extracting a clock and an FIFO 2 receiving the transmission data D1 by using the extracted clock CLK1 and reading and outputting a input data by a transmission clock CLK2 for transmission of the output of a modulation section MOD and outputting it are added to a pre-stage of the modulation section MOD at the sender side. Then a speed V1 of the input data D1 is selected larger than a transmission speed V. of the output of the modulation section, and write/read address of the FIFO 2 is controlled by using an address control means 3 so that an error of a reception data due to under run/over run of transmission reception caused by the absolute capacity of the FIFO 2 and a difference between both the speeds is eliminated.</p> |
