发明名称 CIRCUIT FOR GENERATING DISCRIMINATION LEVEL VOLTAGE
摘要 CIRCUIT FOR GENERATING DISCRIMINATION LEVEL VOLTAGE A circuit for generating a discrimination level voltage which is used as a reference voltage to discrlminate between two logic levels adjacent to each other in input signals which generally can be in a state corresponding to one of a plurality of different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity of the discrimination level and the frequency at which the levels of the input signals lie in the lower half of the vicinity of the discrimination level are compared, and the discrimination level is controlled so that the above two frequencies are the same.
申请公布号 CA1306774(C) 申请公布日期 1992.08.25
申请号 CA19890591121 申请日期 1989.02.15
申请人 FUJITSU LIMITED 发明人 KAWAI, MASAAKI;WATANABE, HISAKO;OHTSUKA, TOMOYUKI
分类号 H03M5/06;G01R19/165;H03K5/08;H04L1/00;H04L25/03 主分类号 H03M5/06
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